View APW7158_8319023.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . dual synchronous buck pwm controllers the APW7158 has two synchronous buck pwm control- lers with high precision internal references voltage to of- fer accurate outputs. the pwm controllers are designed to drive two n-channel mosfets in synchronous buck topology. the device requires 12v and 5v power supplies. if the 5v supply is not available, the device can offer an optional shunt regulator 5.8v for 5v supply. both outputs have independent soft-start and enable func- tions combined on the ss/en pin. connecting a capaci- tor from each ss/en pin to the ground for setting the soft- start time, and pulling the ss/en pin voltage below 1v to disable regulator. the device also offers 180 phase shift function between out1 and out2. the default switching frequency is 300khz (keep the fs pin open or short to gnd), and the device also provides the programmable switching frequency function to ad- just the switching frequency from 70khz to 800khz. con- necting a resistor from fs pin to gnd increases the switching frequency. conversely, connecting a resistor from fs pin to vcc12 decreases the switching frequency. there is no current sensing or under-voltage sensing on the APW7158. however, it provides a simple short-circuit protection by monitoring the comp1 pin and comp2 pin for over-voltage. when any of two pins exceed their trip point and the condition keeps for 1-2 internal clock cycles (3-6us at 300khz), all regulators are latched off. f e a t u r e s two synchronous buck converters(out1,out2) converter input voltage range up to 12v 0.6v reference for out1 with 0.8% accuracy 3.3v reference for out2 with 0.8% accuracy both outputs have independent soft-start and enable functions internal 300khz oscillator and programmable frequency range from 70 khz to 800khz 180 degrees phase shift etween out1 and out2 short-circuit protection thermally enhanced sop-20 package lead free and green devices available (rohs compliant) a p p l i c a t i o n s g e n e r a l d e s c r i p t i o n graphic cards low-voltage distributed power supplies smps application s i m p l i f i e d a p p l i c a t i o n c i r c u i t p i n c o n f i g u r a t i o n fb 1 1 comp 1 2 comp 2 3 fb 2 4 refin 5 refout 6 ss 1 / en 1 7 ss 2 / en 2 8 vref 9 fs 10 20 vcc 19 boot 1 18 ugate 1 17 vcc 12 16 lgate 1 15 lgate 2 14 pgnd 13 boot 2 12 ugate 2 11 gnd s APW7158 v out1 refin refout ss1/en1 vcc12 vcc v in1 v in2 v out2 v out1 v out2 ss2/en2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 2 symbol parameter rating unit v cc12 vcc12 to gnd voltage - 0.3 to 20 v v cc , separate supply vcc, separate supply to gnd voltage - 0.3 to 5.5 v v ugate1 , v ugate2 , v boot1 , v boot2 ugate1, ugate2, boot1, boot2 to pgnd voltage - 0.3 to 30 v v lgate1 , v lgate2 lgat e1, lgate2 to gnd v oltage - 0.3 to 20 v v fs fs to gnd v oltage - 0.3 to 20 v v refin , v refout , v ref refin, refout, vref to gnd v oltage - 0.3 to v cc v v fb1 , v comp1 , v fb2 , v comp2 fb1, comp1, fb2, comp2 to gnd voltage - 0.3 to v cc v v ss1/en1 , v ss2/en2 ss1/en1, ss2/en2, to gnd voltage - 0.3 to v cc v pgnd to gnd voltage - 0.3 to +0.3 v t a operating temperature range - 20 to + 70 o c t j maximum junction temperature +150 o c t stg storage temperature range - 65 to +150 o c t sdr maximum lead soldering temperature , 10 se conds 260 o c o r d e r i n g a n d m a r k i n g i n f o r m a t i o n a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja junction - to - ambient resistance in free air (note 2) sop - 20 75 o c/w q jc junction - to - case resistance in free air (note 3) sop - 20 20 o c/w note 2 : q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. note 3: the case temperature is measured at the center of the exposed pad on the underside of the sop - 20 package. n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package code k : sop-20 operating ambient temperature range e : -20 to 70 o c handling code tr : tape & reel assembly material g : halogen and lead free device APW7158 k: APW7158 xxxxx xxxxx - date code APW7158 handling code temperature range package code assembly material
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 3 r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 4 ) symbol parameter range unit v cc12 vcc12 supply voltage 10.8 to 13.2 v v cc vcc supply voltage 4.5 to 5.5 v v in converter input voltage 2.2 to 13.2 v v out converter output voltage 0.6 to 5 v i out converter output current 0 to 20 a t a ambient temperatur e range - 20 to 70 o c t j junction temperature range - 20 to 125 o c note 4 : refer to the typical application circuit e l e c t r i c a l c h a r a c t e r i s t i c s operating conditions: v cc = 5v, v cc12 = 12v, t a = - 20 to 70 c . typical valu es are at t a = 25 c . unless otherwise specified. ap w7158 symbol parameter test conditions min . typ . max . unit input supply power out1 and out2 di sabled - 4 - ma i vcc vcc input supply current ugates, lgates c l = 1nf, 300khz - 7 - ma out1 and out2 disabled - 6 - ma i vcc12 vcc12 input supply current ugates, lgates c l = 1nf, 300khz - 50 - ma shunt regulator output voltage 20ma current; equivalent to 300 w resistor from vcc to v cc12 5.6 5.8 6.0 v maximum shunt regulator current - - 60 ma v cc r ising 4.15 4.23 4.4 v v cc f alling 3.9 4.0 4.15 v v cc12 r ising 7.55 7.8 8 v power - on - reset threshold voltage v cc12 f alling 7.1 7.3 7.55 v system accurac y out1 reference voltage - 0.6 - v out1 system accuracy - 0.8 - 0.8 % oscillator oscillator accuracy - 20 - 20 % f s oscillator frequency fs pin is open 240 300 360 khz oscillator adjustment range fs pin: resistor to gnd; resistor to vcc12 70 - 8 00 khz oscillator sawtooth amplitude - 2.1 - v oscillator duty - cycle range 0 - 85 % error amplifier (out1 and out2) open - loop gain r l = 10k w to ground - 85 - db open - loop bandwidth c l = 100pf, r l = 10k w to ground - 15 - mhz slew rate c l = 100pf, r l = 10k w to ground - 4 - v/ s error amplifier offset voltage comp1/2 to fb1/2; compare to internal vref/refin - 2 - mv
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 4 operating conditions: v cc = 5v, v cc12 = 12v, t a = - 20 to 70 c . typical valu es are at t a = 25 c . unless otherwise specified. apw715 8 symbol parameter test condition s min. typ. max. unit error amplifier (out1 and out2) (cont.) maximum comp high v oltage comp1/2 , r l = 10k w to ground; (may trip short - circuit) - v cc - v comp source current comp1/2, v comp =2v - - 50 - ma comp sink current comp1/2, v comp =2v - 45 - ma protection and monitor short - circuit protection threshold v comp1 and v comp2 rising - 3.3 - v short - circu it protection filter time based on internal oscillator clock frequency (nominal 300khz = 3.3 m s clock period) 1 - 2 clock pulses vref v ref vref output voltage - 3.3 - v vref output accuracy - 0.8 - 0.8 % vref source current - - 2.0 ma refout v refo ut refout output voltage determined by refin voltage 0.6 - 3.3 v refout offset voltage - 10 - 10 mv refout source current - - 20 ma refout sink current - - 0.48 ma refout output capacitance 0.4 0.1 2.2 f enable/soft - start (ss/en 1,2) high level input voltage 2 - - v enable threshold voltage low level input voltage - - 0.4 ss/en pin soft - start current - - 30 - a soft - start high voltage end of ramp - 3.5 - v gate drivers out1 gate driver source v ugate1 , v lgate1 =3v, v boot = 12 v - 1.8 - a out2 gate driver source v ugate2 , v lgate2 =3v, v boot = 12 v - 1 - a out1 gate driver sink v ugate1 , v lgate1 =3 v , v cc12 =12v - 2.5 - w out2 gate driver sink v ugate 2 , v lgate 2 =3 v , v cc12 =12v - 4 - w e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 5 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 3.25 3.26 3.27 3.28 3.29 3.3 3.31 3.32 3.33 3.34 3.35 0 5 10 15 20 3.28 3.29 3.3 3.31 3.32 0 0.5 1 1.5 2 s o u r c e c u r r e n t ( m a ) s o u r c e c u r r e n t ( m a ) refout voltage, v refout (v) vref voltage, v ref (v) r e f o u t v o l t a g e v s . s o u r c e c u r r e n t v r e f v o l t a g e v s . s o u r c e c u r r e n t 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 0 2 4 6 8 10 12 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 0 2 4 6 8 10 12 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 0 2 4 6 8 10 12 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 0 2 4 6 8 10 12 ugate1 voltage, v ugate1 (v) ugate1 voltage, v ugate1 (v) sink current (a) source current (a) ugate1 source current vs. voltage ugate1 sink current vs. voltage sink current (a) source current (a) lgate1 source current vs. voltage lgate1 sink current vs. voltage lgate1 voltage, v lgate1 (v) lgate1 voltage, v lgate1 (v)
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 6 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 2 4 6 8 10 12 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 2 4 6 8 10 12 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 2 4 6 8 10 12 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 2 4 6 8 10 12 ugate2 voltage, v ugate2 (v) ugate2 voltage, v ugate2 (v) source current (a) sink current (a) ugate2 source current vs. voltage ugate2 sink current vs. voltage b o o t = 1 2 v b o o t = 1 2 v lgate2 voltage, v lgate2 (v) lgate2 voltage, v lgate2 (v) sink current (a) source current (a) lgate2 sink current vs. voltage 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 f s t o g n d 0 10 20 30 40 50 60 3 3.5 4 4.5 5 5.5 6 6.5 7 s h u n t r e g u l a t o r v o l t a g e ( v ) sink current (ma) s w i t c h i n g f r e q u e n c y ( k h z ) fs resistance (k w ) f s t o v c c 1 2 f s r e s i s t a n c e v s . s w i t c h i n g f r e q u e n c y lgate2 source current vs. voltage s h u n t r e g u l a t o r s i n k c u r r e n t v s . v o l t a g e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 7 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) 590 592 594 596 598 600 602 604 606 608 610 0 25 50 75 100 125 150 3.25 3.26 3.27 3.28 3.29 3.3 3.31 3.32 3.33 3.34 3.35 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 0 1 2 3 4 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 c o m p v o l t a g e ( v ) j u n c t i o n t e m p e r a t u r e ( c ) vref voltage (v) source current (ma) c o m p s o u r c e c u r r e n t v s . v o l t a g e vref voltage vs. junction temperature j u n c t i o n t e m p e r a t u r e ( c ) fb voltage (mv) fb voltage vs. junction temperature c o m p v o l t a g e ( v ) sink current (ma) c o m p s i n k c u r r e n t v s . v o l t a g e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 8 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 2 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . o ut1 power on ch2: v cc , 2v/div, dc ch3: v out1 , 2v/div, dc time: 5ms/div ch1: v cc12 , 5 v/div, dc ch4: v ss1/en1 , 2v/div, dc 1 4 3 2 v cc12 v cc v ss1/en1 v out1 1 4 2 3 ch2: v cc , 2v/div, dc ch3: v out2 , 2v/div, dc time: 5ms/div ch1: v cc12 , 5 v/div, dc ch4: v ss2/en2 , 2v/div, dc v cc12 v cc v out2 v ss2/en2 o ut2 power on vref output voltage power on 1 4 ch2: v cc , 2v/div, dc ch3: v ref , 2v/div, dc time: 5ms/div ch1: v cc12 , 5 v/div, dc ch4: v ss2/en2 , 2v/div, dc 3 2 v cc12 v cc v ss2/n2 v ref phase shift 180 d egress 1 4 2 3 ch2: v lgate1 , 10 v/div, dc ch3: v ugate2 , 10 v/div, dc time: 2 g s/div ch1: v ugate1 , 10 v/div, dc ch4: v lgate2 , 10 v/div, dc v ugate1 v lgate1 v ugate2 v lgate2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 9 o p e r a t i n g w a v e f o r m s ( c o n t . ) refer to the typical application circuit. the test condition is v in =12v, t a = 25 o c unless otherwise specified. out1 short circuit protection 1 3 2 ch2: v ss1/en1 , 2v/div, dc ch3: v ugate1 , 20v/div, dc time: 20 g s/div ch1: v comp1 , 2v/div, dc v comp1 v ss1/en1 v ugate1 out2 short circuit protection 1 3 2 ch2: v ss2/en2 , 2v/div, dc ch3: v ugate2 , 20v/div, dc time: 20 g s/div ch1: v comp2 , 2v/div, dc v comp2 v ugate2 v ss2/en2 o ut2 load transient 2 3 ch2: v out2 , 200mv/div, ac ch3: i out2 , 10a/div, dc time: 50 g s/div ch1: v out1 , 200mv/div, ac i out2 =0a->10a->0a i out2 rising/falling time=5 g s v out1 v out2 i out1 1 out1 load transient 1 2 3 ch2: v out2 , 200mv/div, ac ch3: i out1 , 10a/div, dc time: 50 g s/div ch1: v out1 , 200mv/div, ac i out1 =0a->10a->0a i out1 rising/falling time=5 g s v out1 i out1 v out2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 1 0 o p e r a t i n g w a v e f o r m s ( c o n t . ) r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 2 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . 1 2 ugate1 voltage falling ch2: v phase1 , 10v/div, dc ch3: v lgate1 , 10v/div, dc time: 100ns/div ch1: v ugate1 , 10v/div, dc 3 v ugate1 v phase1 v lgate1 ugate1 voltage rising 1 3 2 ch2: v phase1 , 10v/div, dc ch3: v lgate1 , 10v/div, dc time: 100ns/div ch1: v ugate1 , 10v/div, dc v ugate1 v phase1 v lgate1 ugate2 voltage rising 1 2 ch2: v phase2 , 10v/div, dc ch3: v lgate2 , 10v/div, dc time: 100ns/div ch1: v ugate2 , 10v/div, dc 3 v ugate2 v phase2 v lgate2 ugate2 voltage falling 1 2 3 ch2: v phase2 , 10v/div, dc ch3: v lgate2 , 10v/div, dc time: 100ns/div ch1: v ugate2 , 10v/div, dc v ugate2 v phase2 v lgate2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 1 1 p i n d e s c r i p t i o n pin no. name f unction 1 fb1 these pins are the inverting inputs of the error amplifiers of their respective regulators. they are used to set the output voltage and the compensation components. 2 comp1 these pins are the outputs of error amplifiers of t heir respective regulators. they are used to set the compensation components. 3 comp2 these pins are the outputs of error amplifiers of their respective regulators. they are used to set the compensation components. 4 fb2 these pins are the inverting inpu ts of the error amplifiers of their respective regulators. they are used to set the output voltage and the compensation components. 5 refin this pin is the reference input voltage of error amplifier of out2 . it also provides the voltage into a buffer , whi ch is out on the refout pin. 6 refout this pin provides a buffed voltage , which is from refin pin. a 0.1 m f capacitor to ground is recommended for stability. 7 ss1/en1 8 ss2/en2 these pins provide two functions. connect a capacitor to the gnd for setting the soft - start time. use an open drain logic signal to pull the ss/en pin low to disable the respective output, lea ve it open to enable the respective output. 9 vref this pin provides a 3.3v reference voltage , which can be used by the refin pin or other ics as a voltage reference. a 1 m f capacitor to ground is recommended for stability. 10 fs this pin is u sed to adjust the switching frequency. connecting a resistor from fs pin to gnd increases the switching frequency. conversely, connecting a resistor from this pin to vcc12 reduces the switching frequency. 11 gnd this pin is the signal ground pin for the i c . 12 ugate2 these pins provide the gate driver for the upper mosfets of out1 and out2 respectively. 13 boot2 these pins provide the bootstrap voltage to the gate driver for driving the upper mosfets. a boostrap circuit may be used to create a boot volt age . 14 pgnd this pin is the power ground for the gate driver circuits . it should be tied to the gnd. 15 lgate2 16 lgate1 these pins provide the gate driver for the lower mosfets of out1 and out2 . 17 vcc12 power s upply i nput p in. connect a nominal 12v power supply to this pin for the gate driver circuits . a decoupling capacitor (1 to 10 m f) to gnd is recommended for noise decoupling. 18 ugate1 these pins provide the gate driver for the upper mosfets of out1 and out2 respectively. 19 boot1 these pins provide the bootstrap voltage to the gate driver for driving the upper mosfets. a boostr ap circuit may be used to create a boot voltage . 20 vcc power s upply i nput p in. connect a nominal 5v power supply to this pin for the control circuit s , or connect a resistor (nominally 300 w ) to vcc12 to function this pin as a shunt regulator (typical 5.8v ). a decoupling capacitor (1 to 10 m f) to gnd is recommended for noise decoupling.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 1 2 b l o c k d i a g r a m vcc vref vcc 12 ss1/en1 ss2/en2 comp 1 comp 2 fb 1 refin fb 2 gnd pgnd refout fs lgate 2 ugate 2 boot 2 lgate 1 ugate 1 boot 1 power-on-reset and control 5 . 8 v 3 . 3 v bias current 0 . 6 v 3 . 3 v gate control logic 1 gate control logic 2 oscillator 0 . 6 v 3 . 3 v 1 - 2 clock cycle filter 30 m a 30 m a
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 1 3 t y p i c a l a p p l i c a t i o n c i r c u i t vcc vcc12 vref comp1 fb1 comp2 fb2 refin refout vref fs/sync ss1/en1 ss2/en2 gnd pgnd lgate2 ugate2 boot2 lgate1 ugate1 boot1 APW7158 vcc12 300 w 300 w 5.1 w r3 r1 12v r2 c6 22nf c13 5.6nf 12v r4 8.2k w c9 33nf r7 12k w r6 1k w r5 1.1k w c16 5.6nf r9 12k w r10 8.2k w r11 1k w r16 0 w r13 360k w c15 33nf c17 22nf vcc12 c27 0.1 m f c18 0.1 m f c21 1 m f c19 0.1 m f c20 0.1 m f c24 0.1 m f c25 0.1 m f c1 10 m f mlcc c2 10 m f mlcc c3 2200 m f ale c4 2200 m f ale c14 2200 m f c8 0.1 m f c10 1 m f c26 0.1 m f c22 10 m f mlcc c23 10 m f mlcc c7 1 m f c5 1 m f c11 2200 m f ale c12 2200 m f ale r8 2.2 w r14 2.2 w c28 2200 m f c29 1 m f c31 2200 m f ale c30 2200 m f ale d1 bat54a d2 bat54a q1 apm2510n q2 apm2566n q3 apm2510n q4 apm2566n d3 bscd24 d4 bscd24 12v_fltr 12v_fltr l1 1 m h l2 7.3 m h l3 7.3 mh r12 nc r17 nc r15 nc v out1 v out2 v out1 5v v out2 3.3v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 1 4 f u n c t i o n d e s c r i p t i o n soft-start/enable shunt regulator the APW7158 must have two power supplies v cc (5v) and v cc12 (12v) to drive the ic; v cc (5v) is for the control circuits and v cc12 (12v) is for the drivers of outputs. the shunt regulator is designed for these systems like figure 3 that do not have a 5v power supply; the range of the shunt regulator voltage (5.8v, typical) is designed over the usual range 4.5v to 5.5v of typical 5v power supplies. connect a resistor from vcc12 pin to vcc pin for shunt regulator and for the supply current; the typical value, 300 w of the resistor is recommended. phase shift the device offers 180 phase shift function between out1 and out2. the advantage of phase shift is to avoid over- lapping the switching current spikes of the two channels or interaction between the channels; it also reduces the rms current of the input capacitors, allowing fewer caps to be employed. however, because the phase shift be- tween the rising edge of v lgate1 and v lgate2 (see figure 1.) depends on the duty cycles, the falling edges of the two channels might overlap. therefore, the user should check it. figure 1. phase of v lgate2 with respect to rising edge of v lgate1 0 o 180 o v ugate 1 v lgate 1 v ugate 2 v lgate 2 the ss/en pins control the soft-start and enable or dis- able the controller. the two regulators have independent soft-start and enable functions. connect a soft-start ca- pacitor from each ss/en pin to the gnd to set the soft- start interval, and an open drain logic signal for each ss/ en pin will enable or disable the respective output. figure 2 shows the soft-start interval. when both v cc and v cc12 reach their power-on-reset threshold 4.23v and 7.8v, a 30 m a current source starts to charge the capacitor. when the v ss reaches the enabled threshold about 1v, the internal 0.6v reference starts to rise and follows the v ss ; the error amplifier output (v comp ) suddenly raises to 1.1v, which is the valley of the oscillator?s triangle wave, and leads the v out to start up. until the v ss reaches about 3.0v, the internal reference completes the soft-start interval and reaches to 0.6v, and then v out is in regulation. the v ss still rises to 3.5v and then stops. time voltage t 1 t 2 t 0 v ss / en v out 3 v 1 v figure 2. soft-start interval v 2 i c t t t ss ss 1 2 start soft = - = - where: c ss = external soft-start capacitor i ss = soft-start current = 30 a
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 1 5 f u n c t i o n d e s c r i p t i o n ( c o n t . ) oscillator the APW7158 provides the oscillator switching frequency adjustment. connect a resistor from fs pin to the ground; the nominal 300khz oscillator switching frequency is increased according to the value of the resistor. thus, the adjustment range of the switching frequency is nomi- nal 300khz to 800khz. conversely, connecting a resistor from fs pin to the vcc12 pin reduces the switching fre- quency according to the value of the resistor. thus, the adjustment range of the switching frequency is 70khz to nominal 300khz. (see figure 4.). short-circuit protection the APW7158 has a simple short-circuit protection to monitor comp1 pin and comp2 pin for out1 and out2. when output voltage has a short, the fb pin should start to follow output since it is a resistor divider from the output. the fb pin is the inverting input of error-amp. when fb pin is lower than the error-amp reference, the v comp will rise to increase the duty-cycle of the upper mosfet gate driver, and this allows output to get higher voltage. if the short-circuit condition is long enough, the v comp will ex- ceed the trip point 3.3v and the duty circle will hit the maximum. this means that either over-current or un- der-voltage condition is detected. if any of the v comp1 and v comp2 exceed their trip points and hold over a filter time (1-2 clock cycles of switching frequency), all regulators will shut down and require a por on either of vcc or vcc12 pin to restart. figure 3. optional r for shunt regulator 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 switching frequency ( khz ) f s r e s i s t a n c e ( k [ ) fs to vcc12 fs to gnd figure 4. fs resistance vs. frequency v cc ( 5 . 8 v ) v cc12 r vcc 12 vcc apw 7158 shunt regulator (cont.)
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 1 6 a p p l i c a t i o n i n f o r m a t i o n pwm compensation the output lc filter of a step down converter introduces a double pole, which contributes with ?40db/decade gain slope and 180 degrees phase shift in the control loop. a compensation network between v comp , v fb and v out should be added. the compensation network is shown in fig. 8. the out- put lc filter consists of the output inductor and output capacitors. the transfer function of the lc filter is given by: 1 c esr s c l s c esr s 1 gain out out 2 out lc + + + = the poles and zero of this transfer function are: out lc c l 2 1 f p = out esr c esr 2 1 f p = the flc is the double poles of the lc filter, and fesr is the zero introduced by the esr of the output capacitor. v phase v out l c out esr figure 5. the output lc filter gain f esr f lc frequency -40db/dec -20db/dec figure 6. the lc filter gain & frequency the pwm modulator is shown in figure. 7. the input is the output of the error amplifier and the output is the phase node. the transfer function of the pwm modula- tor is given by: osc in pwm v v gain d = v osc pwm comparator driver driver output of error amplifier v in v phase figure 7. the pwm modulator the compensation circuit is shown in figure 8. it pro- vides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. the transfer function of error amplifier is given by: ? ? ? ? ? + ? ? ? ? ? + = = 3 sc 1 3 r // 1 r 2 sc 1 2 r // 1 sc 1 v v gain out comp amp ? ? ? ? ? + ? ? ? ? ? + + ? ? ? ? ? + + ? ? ? ? ? + + = 3 c 3 r 1 s 2 c 1 c 2 r 2 c 1 c s s 3 c ) 3 r 1 r ( 1 s 2 c 2 r 1 s 1 c 3 r 1 r 3 r 1 r the poles and zeros of the transfer function are: 2 c 2 r 2 1 f 1 z p = 3 c ) 3 r 1 r ( 2 1 f 2 z + p = ? ? ? ? ? + p = 2 c 1 c 2 c 1 c 2 r 2 1 f 1 p 3 c 3 r 2 1 f 2 p p =
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 1 7 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) pwm compensation (cont.) v comp c2 v out r3 v ref c1 v fb - + c3 r2 r1 figure 8. compensation network the closed loop gain of the converter can be written as: amp pwm lc gain gain gain figure 9. shows the asymptotic plot of the closed loop converter gain and the following guidelines will help to design the compensation network. using the below guidelines should give a compensation similar to the curve plotted. a stable closed loop has a -20db/ decade slope and a phase margin greater than 45 degree. 1. choose a value for r1, usually between 1k and 5k. 2. select the desired zero crossover frequency f o : (1/5 ~ 1/10) x f s >f o >f esr use the following equation to calculate r2: 1 r f f v v 2 r lc o in osc d = 3. place the first zero f z1 before the output lc filter double pole frequency f lc . f z1 = 0.75 x f lc calculate the c2 by the equation: 75 . 0 f 2 r 2 1 2 c lc p = 4.set the pole at the esr zero frequency f esr : f p1 = f esr calculate the c1 by the equation: 1 f 2 c 2 r 2 2 c 1 c esr - p = 5. set the second pole f p2 at half the switching frequency and also set the second zero f z2 at the output lc filter double pole f lc . the compensation gain should not ex- ceed the error amplifier open loop gain, check the com- pensation gain at f p2 with the capabilities of the error amplifier. f p2 = 0.5xf o f z2 = f lc combine the two equations will get the following compo- nent calculations: 1 f 2 f 1 r 3 r lc s - = s f 3 r 1 3 c p = gain 0 f lc f esr f p2 =0.5f s f z1 =0.75f lc f o frequency pwm & filter gain compensation gain converter gain f z2 =f lc f p1 =f esr 20log (v in / v osc ) 20log (r2/r1) open loop error amp gain figure 9. converter gain & frequency output inductor selection the inductor value determines the inductor ripple current and affects the load transient response. higher inductor value reduces the inductor?s ripple current and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: in out s out in ripple v v l f v v i - = esr i vout ripple = d
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 1 8 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) where fs is the switching frequency of the regulator. al- though increase the inductor value and frequency reduce the ripple current and voltage, but there is a tradeoff ex- ists between the inductor?s ripple current and the regula- tor load transient response time. a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f s ) also reduces the ripple current and voltage, but it will increase the switch- ing loss of the mosfet and the power dissipation of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maxi- mum output current. once the inductance value has been chosen, select an inductor that is capable of carrying the required peak cur- rent without going into saturation. in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this will result in a larger output ripple voltage. output inductor selection (cont.) output capacitor selection higher capacitor value and lower esr reduce the output ripple and the load transient drop. therefore select high performance low esr capacitors that are intended for switching regulator applications. in some applications, multiple capacitors have to be parallel to achieve the de- sired esr value. a small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors are also must be considered. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. input capacitor selection the input capacitor is chosen based on the voltage rating and the rms current rating. for reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. the maximum rms current rating requirement is approxi- mately i out /2, where i out is the load current. during power up, the input capacitors have to handle large amount of surge current. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. for high frequency decoupling, a ceramic capacitor 1uf can be connected between the drain of upper mosfet and the source of lower mosfet. mosfet selection t h e s e l e c t i o n o f t h e n - c h a n n e l p o w e r m o s f e t s a r e d e - t e r m i n e d b y t h e r d s ( o n ) , r e v e r s e t r a n s f e r c a p a c i t a n c e ( c r s s ) a n d m a x i m u m o u t p u t c u r r e n t r e q u i r e m e n t . t h e l o s s e s i n t h e m o s f e t s h a v e t w o c o m p o n e n t s : c o n d u c t i o n l o s s a n d t r a n s i t i o n l o s s . f o r t h e u p p e r a n d l o w e r m o s f e t , t h e l o s s e s a r e a p p r o x i m a t e l y g i v e n b y t h e f o l l o w i n g : p upper =i out (1+tc)(r ds(on) )d+(0.5)(i out )(v in )(t sw )f s p lower =i out (1+tc)(r ds(on) )(1-d) where i out is the load current tc is the temperature dependency of rds(on) f s is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction losses while the upper mosfet include an additional transition loss. the switching internal, t sw , is a function of the reverse transfer capacitance c rss . the (1+tc) term is to factor in the temperature depen- dency of the r ds(on) and can be extracted from the ?r ds(on) vs temperature? curve of the power mosfet. short circuit protection t h e a p w 7 1 5 8 p r o v i d e s a s i m p l e s h o r t c i r c u i t p r o t e c t i o n f u n c t i o n , a n d i t i s n o t e a s y t o p r e d i c t i t s p e r f o r m a n c e , s i n c e m a n y f a c t o r s c a n a f f e c t h o w w e l l i t w o r k s . t h e r e f o r e , t h e l i m i t a t i o n s a n d s u g g e s t i o n s o f t h i s m e t h o d m u s t b e p r o - v i d e d f o r u s e r s t o u n d e r s t a n d h o w t o w o r k i t w e l l . the short circuit protection was not designed to work for the output in initial short condition. in this case, the short circuit protection may not work, and damage the mosfets. if the circuit still works, remove the short can cause an inductive kick on the phase pin, and it may damage the ic and mosfets. if the resistance of the short is not low enough to cause protection, the regulator will work as the load has
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 1 9 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) increased, and continue to regulate up until the mosfets is damaged. the resistance of the short should include wiring, pcb traces, contact resistances, and all of the return paths. the higher duty cycle will give a higher comp voltage level, and it is easy to touch the trip point. the compensa- tion components also affect the response of comp voltage; smaller caps may give a faster response. the output current has faster rising time during short; the comp pin will have a sharp rise. however, if the cur- rent rises too fast, it may cause a false trip. the output capacitance and its esr can affect the rising time of the current during short. short circuit protection (cont.) layout consideration in high power switching regulator, a correct layout is im- portant to ensure proper operation of the regulator. in general, interconnecting impedances should be mini- mized by using short, wide printed circuit traces. signal and power grounds are to be kept separate and finally combined using ground plane construction or single point grounding. figure 10 illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. components along the bold lines should be placed lose together. below is a check- list for your layout : the metal plate of the bottom of the packages (sop- 20) must be soldered to the pcb and connected to the gnd plane on the backside through several thermal vias. keep the switching nodes (ugate, lgate and phase) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep traces to these nodes as short as possible. the traces from the gate drivers to the mosfets (ugate1, lgate1, ugate2, lgate2) should be short and wide. decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and ss capacitors should be close their pins. the input capacitor should be near the drain of the upper mosfet; the output capacitor should be near the loads. the input capacitor gnd should be close to the output capacitor gnd and the lower mosfet gnd. the drain of the mosfets (vin and phase nodes) should be a large plane for heat sinking. figure 10. layout guidelines v in v out q1 l1 c in APW7158 l o a d boot vcc12 ss fb gnd c ss c vcc c boot q2 c out vcc lg ug pgnd c vcc12 vref c vref refout c refout
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 2 0 p a c k a g e i n f o r m a t i o n s o p - 2 0 0 l view a 0 . 2 5 seating plane gauge plane note : 1. follow from jedec ms-013 ac. 2. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. dimension "e" does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 10 mil per side. d e 1 e e b a a 1 a 2 s y m b o l min. max. 2.65 0.10 0.20 0.33 0.30 a a1 c d e e1 e h l millimeters b 0.31 0.51 sop-20 0.25 0.75 0.40 1.27 min. max. inches 0.104 0.004 0.012 0.020 0.008 0.013 0.010 0.030 0.016 0.050 0 0 o 8 o 0 o 8 o 0.012 1.27 bsc 0.050 bsc 2.05 0.081 a2 12.60 13.00 0.496 0.512 10.10 10.50 0.398 0.413 7.40 7.60 0.291 0.299 see view a c h x 4 5 o
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 2 1 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 24.40+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 24.0 ? 0.30 1.75 ? 0.10 11.5 ? 0.10 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 sop - 20 4.0 ? 0.10 12.0 ? 0.10 2.0 ? 0.10 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.40 10.9 ? 0.20 13.3 ? 0.20 3.1 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s d e v i c e s p e r u n i t package type unit quantity sop - 20 tape & reel 1 000 a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 2 2 t a p i n g d i r e c t i o n i n f o r m a t i o n c l a s s i f i c a t i o n p r o f i l e s o p - 2 0 user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 2 3 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ 125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a115 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - a u g . , 2 0 0 9 a p w 7 1 5 8 w w w . a n p e c . c o m . t w 2 4 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

▲Up To Search▲

Price & Availability of APW7158

	To Download APW7158 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .